There have been remarkable increases in capacity and speed of semiconductor memory devices including a dynamic RAM. In a DDR SDRAM (Double Data Rate Synchronous DRAM) in particular, internal operations are pipelined, and commands that have been supplied from an outside in synchronization with a clock are sequentially executed. Together with the sequential execution of the commands, it is arranged that data transfer is performed at a rate twice as the frequency of the clock, thereby implementing a high-speed system operation. In the DDR SDRAM or the like, a DLL (Delay Locked Loop) circuit is employed. Then, an internal circuit is operated in synchronization with the clock supplied from the outside. A high-speed data transfer is thereby implemented. Patent Document 1, for example, describes a memory device in which a skew between a system clock supplied from an outside and a data strobe terminal (DQS terminal) or a data terminal (DQ terminal) is minimized, using a DLL.
On the other hand, reduction in power consumption of a semiconductor memory device has been demanded in a server or the like as well as a notebook PC that operates on a battery. However, since the DLL must cause the clock to be constantly operated at a high speed, this high speed of the clock may lead to an increase in power consumption. On contrast therewith, page 37 of Non-patent Document 1 describes that provision of a DLL-off mode by which the DLL is turned off is specified in a DDR3 SDRAM. The DDR3 SDRAM is the latest DDR SDRAM standard.
The DLL-off mode specified in this Non-patent Document 1 will be described. FIG. 1 is a timing diagram about a DLL-on mode and the DLL-off mode in the DDR3 SDRAM. Referring to FIG. 1, “CK” denotes a system clock signal that is supplied to a CK terminal of the DDR3 SDRAM from a memory controller, “/CK” is an inverted signal of the “CK” signal, which is supplied to a “/CK terminal”. FIG. 1 shows the CK signal by a solid line and the /CK signal by a broken line. “Command” denotes a command that is supplied to the DDR3 SDRAM from the memory controller, and “Bank Add” and “Col Add” respectively denote a bank address and a column address when the command is supplied to the DDR3 SDRAM. Data output from a DQ terminal (data terminal) of the DDR3 SDRAM, data strobe signals output from a DQS terminal (data strobe terminal) and a /DQS terminal (inverted data strobe terminal) of the DDR3 SDRAM at a time of receiving a read command are respectively indicated as “DQ”, “DQS”, and “/DQS”. The data strobe signal DQS is indicated by a solid line, while the data strobe signal /DQS is indicated by a broken line. FIG. 1 shows the DQ signal and the DQS signal that are output from the DDR3 SDRAM at a time of receiving the read command when the DDR3 SDRAM is set to a DLL-on mode and when the DDR3 SDRAM is set to the DLL-off mode. A CAS latency CL is set to six, while an additive latency (Additive Latency) AL is set to 0.
Referring to FIG. 1, the read command is supplied to the DDR3 SDRAM at a rising edge at a timing T0. As described above, the CAS latency is six, and the additive latency is zero in the DLL-on mode. Thus, the DQS terminal outputs a low level for a certain period of time as a read preamble, in advance. Then, the DQS signal rises in synchronization with a rise of a sixth clock of the system clock at a timing T6. Then, the DQS signal repeats a toggling operation in synchronization with the system clock until a burst output is completed. During that period, the data are output from the DQ terminal, in synchronization with a rise and a fall of the DQS terminal. In the case of the DLL-on mode, the DQS signal output from the DDR SDRAM is synchronized with the system clock signal CK and the /CK signal supplied from the memory controller and a DLL circuit. Thus, a phase deviation is small.
On the other hand, in the DLL-off mode, an internal clock generated inside the DDR SDRAM from the system clock supplied from the memory controller is not phase adjusted with the system clock signal. Thus, the phase of the DQS signal generated from the internal clock is also deviated from the system clock. The magnitude of the deviation depends on the magnitude of a delay time of circuits inside the DDR SDRAM. The standard of the DDR3 SDRAM described in Non-patent Document 1 defines that the clock latency is fixed at six, and the DQS signal starts to be output based on a rise of the system clock at a timing t5 one clock earlier than the data output in the DLL-on mode. However, the internal clock has a phase delay with respect to the system clock supplied from an outside. Thus, in the actual DDR SDRAM, data output after receiving the read command is started at substantially the same time as in the DLL-on mode at the earliest or rather later than in the DLL-on mode. The period of time from the rise of the system clock at the timing T5, which is one clock earlier than the timing T6 determined by the CAS latency in the DDR-on mode, to start of the data output is indicated by tDQSCK (DLL off).
Now, read times of read data in the DLL-on mode and the DLL-off mode will be described. In the DDR3, a command and an address are given simultaneously. Thus, a time tAA (Address Access delay time) taken from determination of the address to start of output of the read data is given by Expression (1) or (2).DLL-on tAAmin=CL*tCKmin+tDQSCKmin(DLL on)  Expression (1)DLL-off tAAmin=(CL−1)*tCKmin+tDQSCKmin(DLL off)  Expression (2)
Expression (1) gives the minimum value of the time tAA in the DLL-on mode. CL indicates the value of the CAS latency, tCKmin indicates the minimum value of one cycle of the system clock, tDQSKmin (DLL on) indicates the minimum value of the phase error of the DQS output signal with respect to the system clock input signal in the DLL-on mode. In the DLL-on mode, the DQS signal is synchronized with the system clock signal by the DLL circuit. Thus, even if the time tDQSCK (DLL on) is varied, the time tDQSCK assumes a small value on the order of at most −400 to 400 ps. Further, the time tDQSCK (DLL on) is varied in both positive and negative directions with respect to zero. Accordingly, the minimum value of the time tDQSCKmin (DLL on) assumes the value on the order of −400 to −200 ps.
Expression (2) gives the minimum value of the time tAA in the DLL-off mode. In Expression (2), tDQSCKmin (DLL off) indicates the minimum value of the delay time of the DQS output signal with respect to the system clock. In the DLL-off mode, the phase of the DQS output signal is not adjusted with respect to the system clock, and the DQS output signal is output with its phase kept delayed from the system clock. Accordingly, the time tDQSCK (DLL off) constantly assumes a positive value, and the minimum value of the time tDQSCKmin (DLL off) assumes a large value on the order of 2000 ps. Further, the time tDQSCK (DLL off) constantly assumes the positive value, and output of the DQS signal is delayed. Thus, the standard of the DDR3 defines that the edge of the clock that serves as a reference as in the DLL-off mode is based on CL-1, which is one cycle before the edge of the clock in the case of the DLL-on mode, as shown in Expression (2) described above.
FIG. 1 assumes the standard of the DDR3-800 using the system clock (bus clock) of MAX 400 MHz. Thus, when the minimum value tCKmin is set to 2500 ps, the minimum value tDQSCKmin (DLL on) is set to −400 ps, and the minimum value tDQSCKmin (DLL off) is set to 2000 ps, the minimum value DLL-on tAAmin assumes 14. 6 ns, and the minimum value DLL-off tAAmin assumes 14. 5 ns. Thus, it can be seen that the minimum value tAAmin does not greatly differ between the DLL-on mode and the DLL-off mode.
Patent Document 1:
JP Patent Kokai Publication No. JP2005-332548A
Non-Patent Document 1:
JEDEC STANDARD DDR3 SDRAM Specification, JESD79-3B, April, 2008, JEDEC Solid State Technology Association (JEDEC SOLID STATE TECHNOLOGY ASSOCIATION), page 37